Copyright 2012-2026 / Enjoy-Digital & LiteX developers
Welcome to LiteX!
The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs, to explore various digital design architectures and create full FPGA based systems.
LiteX SoC builder framework quick tour/overview: Slides
Want to get started and/or looking for documentation? Make sure to visit the Wiki!
Want development notes from building FPGA SoCs with LiteX? Visit the LiteX Notes blog!
Working with an AI agent? LiteX is agent-ready: an AGENTS.md in every repository of the ecosystem, an MCP server (litex_mcp) to drive a SoC and agent skills (a Claude Code plugin): see LiteX for AI agents.
A question or want to get in touch? Join us on Discord or on our IRC channel: [#litex at irc.libera.chat].
LiteX provides all the common components required to easily create an FPGA Core/SoC:
- :heavy_check_mark: Buses and Streams (Wishbone, AXI, Avalon-ST) and their interconnect.
- :heavy_check_mark: Simple cores: RAM, ROM, Timer, UART, JTAG, GPIO, SPI, I2C, PWM, video, USB, HyperRAM, etc...
- :heavy_check_mark: Complex cores through the ecosystem of cores: LiteDRAM, LitePCIe, LiteEth, LiteSATA, LiteNVMe, etc...
- :heavy_check_mark: Various CPUs & ISAs: RISC-V (VexRiscv, VexiiRiscv, NaxRiscv, Rocket, SERV, ...), OpenRISC, LM32, POWER, MIPS, the hard CPUs of Zynq, Agilex and Cyclone V, X86 (through a PCIe), etc...
- :heavy_check_mark: Mixed languages support with VHDL/Verilog/SystemVerilog/Amaranth/Spinal-HDL/etc... integration capabilities.
- :heavy_check_mark: Powerful debug infrastructure through the various bridges and LiteScope.
- :heavy_check_mark: Direct/Fast simulation through Verilator.
- :heavy_check_mark: Build backends for open-source and vendor toolchains (Xilinx, Intel, Lattice, Gowin, Efinix, CologneChip, Anlogic, Microsemi, QuickLogic).
- :heavy_check_mark: And a lot more... :)
Typical LiteX design flow:
+---------------+
|FPGA toolchains|
+----^-----+----+
| |
+--+-----v--+
+-------+ | |
| Migen +--------> |
+-------+ | | Your design
| LiteX +---> ready to be used!
| |
+----------------------+ | |
|LiteX Cores Ecosystem +--> |
+----------------------+ +-^-------^-+
(Eth, SATA, DRAM, USB, | |
PCIe, Video, etc...) + +
board target
file file
Your design is two Python files: the platform describes the board (pins, clocks, connectors, toolchain, programmer) and the target describes your SoC (CPU, memories, peripherals, cores from the ecosystem); LiteX-Boards has 250+ of them. The Builder generates the Verilog and the constraints, runs the toolchain (or Verilator), builds the BIOS and writes the software support: csr.h, soc.h, mem.h, memory.x, csr.csv/json/svd, the device trees. The host tools (litex_term, litex_server and litex_cli through a UART, JTAG, Ethernet or PCIe bridge, LiteScope, GDB) then control and debug the running SoC.
LiteX's cores ecosystem
LiteX already supports various softcores CPUs: VexRiscv, Rocket, LM32, Mor1kx, PicoRV32, BlackParrot and is compatible with the LiteX's Cores Ecosystem:
This is the beginning of the README. Read the rest at the original. Read the full README ↗
