Copyright 2012-2026 / Enjoy-Digital & LiteX developers

Welcome to LiteX!

The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs, to explore various digital design architectures and create full FPGA based systems.

LiteX SoC builder framework quick tour/overview: Slides

Want to get started and/or looking for documentation? Make sure to visit the Wiki!

Want development notes from building FPGA SoCs with LiteX? Visit the LiteX Notes blog!

Working with an AI agent? LiteX is agent-ready: an AGENTS.md in every repository of the ecosystem, an MCP server (litex_mcp) to drive a SoC and agent skills (a Claude Code plugin): see LiteX for AI agents.

A question or want to get in touch? Join us on Discord or on our IRC channel: [#litex at irc.libera.chat].

LiteX provides all the common components required to easily create an FPGA Core/SoC:

• :heavy_check_mark: Buses and Streams (Wishbone, AXI, Avalon-ST) and their interconnect.
• :heavy_check_mark: Simple cores: RAM, ROM, Timer, UART, JTAG, GPIO, SPI, I2C, PWM, video, USB, HyperRAM, etc...
• :heavy_check_mark: Complex cores through the ecosystem of cores: LiteDRAM, LitePCIe, LiteEth, LiteSATA, LiteNVMe, etc...
• :heavy_check_mark: Various CPUs & ISAs: RISC-V (VexRiscv, VexiiRiscv, NaxRiscv, Rocket, SERV, ...), OpenRISC, LM32, POWER, MIPS, the hard CPUs of Zynq, Agilex and Cyclone V, X86 (through a PCIe), etc...
• :heavy_check_mark: Mixed languages support with VHDL/Verilog/SystemVerilog/Amaranth/Spinal-HDL/etc... integration capabilities.
• :heavy_check_mark: Powerful debug infrastructure through the various bridges and LiteScope.
• :heavy_check_mark: Direct/Fast simulation through Verilator.
• :heavy_check_mark: Build backends for open-source and vendor toolchains (Xilinx, Intel, Lattice, Gowin, Efinix, CologneChip, Anlogic, Microsemi, QuickLogic).
• :heavy_check_mark: And a lot more... :)

Typical LiteX design flow:

                                      +---------------+
                                      |FPGA toolchains|
                                      +----^-----+----+
                                           |     |
                                        +--+-----v--+
                       +-------+        |           |
                       | Migen +-------->           |
                       +-------+        |           |        Your design
                                        |   LiteX   +---> ready to be used!
                                        |           |
              +----------------------+  |           |
              |LiteX Cores Ecosystem +-->           |
              +----------------------+  +-^-------^-+
               (Eth, SATA, DRAM, USB,     |       |
                PCIe, Video, etc...)      +       +
                                         board   target
                                         file    file

Your design is two Python files: the platform describes the board (pins, clocks, connectors, toolchain, programmer) and the target describes your SoC (CPU, memories, peripherals, cores from the ecosystem); LiteX-Boards has 250+ of them. The Builder generates the Verilog and the constraints, runs the toolchain (or Verilator), builds the BIOS and writes the software support: csr.h, soc.h, mem.h, memory.x, csr.csv/json/svd, the device trees. The host tools (litex_term, litex_server and litex_cli through a UART, JTAG, Ethernet or PCIe bridge, LiteScope, GDB) then control and debug the running SoC.

LiteX's cores ecosystem

LiteX already supports various softcores CPUs: VexRiscv, Rocket, LM32, Mor1kx, PicoRV32, BlackParrot and is compatible with the LiteX's Cores Ecosystem:

Name	Build Status	Description
LiteX-Boards		Boards support
LiteDRAM		DRAM
LiteEth		Ethernet
LitePCIe		PCIe
LiteNVMe		NVMe
LiteSATA		SATA
LiteSDCard		SD card
LiteICLink

Examples of designs built with LiteX:

Custom PCIe SDI Capture/Playback board built around LitePCIe and integrated with LiteX, allowing full control of the SDI flow and very low latency. Alternative firmware/gateware for the SDS1104X-E Scope: HBM2 test infrastructure on Forest Kitten 33:

To discover more products/projects built with LiteX, visit the projects page.

Try it in ten minutes

python3 -m venv ~/litex-venv && source ~/litex-venv/bin/activate
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
chmod +x litex_setup.py
./litex_setup.py --init --install --config=standard   # Migen, LiteX, the cores, the boards, the CPUs
./litex_setup.py --gcc=riscv                           # the RISC-V compiler for the BIOS and software
pip3 install meson ninja
litex_sim --cpu-type=vexriscv                          # a SoC in Verilator, no board needed

That is a VexRiscv SoC running in Verilator, the LiteX BIOS at its prompt in your terminal. Next:

1. Install LiteX: the toolchains, your board, updates, troubleshooting.
2. Create a minimal SoC: the same SoC on your board, from a 40-line Python file.
3. Write firmware for it: the bare-metal demo, built and loaded over the serial port.
4. Control it from the host: read and write the SoC from Python scripts.
5. Look inside with LiteScope: a logic analyzer inside the design.
6. Debug the CPU with GDB: breakpoints in the firmware over JTAG.

By combining LiteX with the ecosystem of cores, creating complex SoCs becomes a lot easier than with traditional approaches while providing better portability and flexibility: Here is for example a Multi-core Linux Capable SoC based on VexRiscv-SMP CPU, LiteDRAM, LiteSATA built and integrated with LiteX, running on a cheap repurposed Acorn CLE215+ Mining Board: For more info, have a look at Linux-on-LiteX-Vexriscv project and try running Linux on your FPGA board!

LiteX's digital logic is currently described with Migen which does not prevent users to create mixed language projects:

• It's very common and easy to integrate VHDL/Verilog/SystemVerilog/Amaranth/Spinal-HDL code in LiteX!
• It's also very common to do the opposite and generate the LiteX design as a verilog file and integrate it in a traditional flow.

LiteX was initially developed by Enjoy-Digital to create projects for clients (and we are still using it for that :)) and trying to take the different clients' requirements/needs consideration made, we think, the framework very flexible:

• Some users only want to use it to easily interconnect their existing VHDL/Verilog/SV cores.
• Some users are only interested to reuse the PCIe/Ethernet/SATA/etc cores as regular core and just integrate them in their traditional flow.
• Some users with a hardware background start with the above approaches and then switch later to the full Python flow since find it more efficient.
• Some users with a software background and fluent with Python start playing with FPGAs while they would probably never touch FPGA otherwise :)
• Etc...

We are well aware that everyone has a different background, so it's up to you to pick the right approach with LiteX that will be convenient for you! The LiteX approach describes the way we build with it.

We share this project under a permissive BSD 2-Clause License, inspired by our fantastic community and supportive clients. If LiteX benefits your research, hobby, or commercial projects, we kindly ask for your positive collaboration and respect for the effort involved. The framework is also far from perfect and we'll be happy to have your feedback or/and contributions. Have fun! :wink:

Where to go next

Build your SoC	Add a new board, Add a new core, Add a new CPU, Reuse an existing core, Create a complex SoC, Create a PCIe SoC, Export to Verilog, Simulate your SoC, Load and flash, LiteX on the Acorn CLE 215+
Run software on it	OSes ecosystem, BIOS, MicroPython, Zephyr, Linux
How LiteX works	, , , / / buses, ,

2026.08 highlights

• More ways to build SoCs: Intel Cyclone V/Agilex HPS integration, Gowin AE350 improvements, native AXI/AXI-Lite HyperRAM, and broader framebuffer memory support.
• New hardware building blocks: FPGA temperature monitors, AP Memory PSRAM and Gowin HyperRAM, SPI/parallel LCD, OV5640 camera capture, and I2S audio.
• Better connectivity: packet streams with byte-valid final words, new LiteEth 1000BASE-X/SGMII PHY options, and LitePCIe protocol and DMA improvements.
• More boards and targets, including ModRetro M64/Chromatic, Sipeed Tang Mega 60K, and new Cyclone V/Agilex HPS paths.
• A dedicated release helper and PyPI publishing workflow for the LiteX ecosystem.

See CHANGES.md for the full list of fixes, additions, and ecosystem updates. LiteJESD204B has been renamed to LiteJESD204; the old Python package remains as a temporary compatibility shim.

Sponsors/Partners

A huge shoutout to our awesome industrial clients who have given us the green light to incorporate some of the developments we initially created for them directly into LiteX! These innovative developments often provide the building blocks for the features that the wider community can then use and improve upon. Your support has been instrumental for the project, and we are incredibly grateful for your partnership. Thanks!

Community

Over the years a friendly community has grown around LiteX and the ecosystem of cores. Feedbacks and contributions have already greatly improved the project, EnjoyDigital still leads the development but it is now a community project and collaborative projects created around/with LiteX can be found at https://github.com/litex-hub.

Contact

E-mail: [email protected]